Specifying the Clock Tree References

ICC uses four clock tree reference lists:

1) one for clock tree synthesis
2)one for boundary cell insertion
3) one for sizing
4) one for delay insertion

By default, each clock tree reference list constains all the buffers and inverters in your technology library.

To fine-tune the results, you can restrict the set of buffers and inverters used for one or more of these operations. For Example, If your clock tree has too many levels, it could be that the clock tree synthesis reference have a loewdrive strength.

To define a clock tree reference list, use the set_clock_tree_references command ( or choose Clock > Set Clock Tree References in the GUI). When you define a clock tree reference list, ensure that the buffers and inverters that you specify have a wide range of drive strengths, so that clock tree synthesis can select the appropriate buffer or inverter for each cluster.

Note:
The clock tree synthesis reference list must include at least one inverter, or clock tree synthesis fails.
If you are using the default clock tree reference list, you must ensure that your target library contains at least one inverter that does not have a dont_use attribute. If you define a clock tree synthesis reference list, you must ensure that it contains at least one inverter.

When you run the set_clock_tree_reference command, ICC verifies that the cells you specify exist in the target libraries, and it generates a warning message if it cannot find a cell.
Note:
For multicorner-multimode designs, ICC checks only the libraries associated with the clock tree synthesis scenario. You need to ensure that the specified clock references exist in the target library specified for the clock tree synthesis scenario.

When you explicitly include a cell in a clock tree reference list, ICC can use the cell for the task associated with the reference list, even if the cell has a dont_use attribute. However, if you set the dont_use attribute on a cell after it is included in a clock tree reference list, ICC honors the dont_sue attribute.

ICC uses this clock tree trference list for all clock trees.

If you issue the set_clock_tree_references command multiple times, the new references you specify are added to existing references. References you previously listed but omitted from a later list are not deleted. To delete references, use the
reset_clock_tree_references command or choose Clock > Set Clock Tree References in the GUI and click Default.

For example, to create a clock tree synthesis reference list, enter
icc_shell> set_clock_tree_reference -references {clk1a6 clk1a9 clk1a15 clk1a27}

ICC uses this clock tree reference list for all clock trees.

Defining Clock Cell Spacing Rules
Clock cells consume more power than cells that are not in the clock network. Clock cells that are clustered together in a small area increase current densities for the power and ground rails, where a potential electromigration problem might occur. One way to avoid the problem is to set spacing requirements between clock cells. You set  the spacing requirements by defining clock cell spacing rules for inverters, buffers, and integrated clock-gating cells in the clock network.

To define clock cell spacing rules, use the set_clock_cell_spacing command and set the mandatory
-x_spacing  and -y_spacing options with a nonzero value. You can optionally restrict the clock cell spacing rules to a collection of library cells by using the -lib_cells option or to a collection of clock names by using the -clocks option.

To report clock cell spacing rules, use the report_clock_cell_spacing command.  The report categorized information into three sections:
1. Clock cell spacing rules set by the -lib_cell option only or by no option.
2. Clock cell spacing rules set by the -clocks option only.
3. Clock cell spacing rules set by both the -lib_cell and -clocks options.

To remove clock cell spacing rules, use the remove_clock_cell_spacing command. You can specify the -lib_cells and -clocks options to remove clock cell spacing constraints from the specified library cells and clocks respectively.

If you use the remove_clock_cell_spacing command with
1) The -lib_cells option
The command removes only the clock cell spacing rules defined by the
set_clock_cell_spacing -lib_cells command with the specified library cells.

2)The -clocks option
The command removes only the clock cell spacing rules defined by the
set_clock_cell_spacing -clocks command with the specified clock names.

3)Both the -lib_cells and -clocks options
The command removes the clock cell spacing rules defined by the
set_clock_cell_spacing -lib_cells -clocks command with the specified library cells and clock names.

4)No option
The command removes the clock cell spacing rules defined by the
set_clock_cell_spacing command with no option.

You use the following steps to reduce electromigration in the design:
1. Afetr obtaining a placement CEL view, set the clock spacing rules by using the set_clock_cell_spacing command.

To remove and report the clock cell spacing rules, use the remove_clock_cell_spacing and report_clock_cell_spacing commands respectively.

2. Perform clock tree synthesis by using either the  compile_clock_tree or optimize_clock_tree command.

3. Check clock cell spacing rule violations by using the check_legality -verbose command.
You should not see any violations if yous set the appropriate clock cell spacing constraints.

Note that the compile_clock_tree , optimize_clock_tree , split_clock_net, and balance_inter_clock_delay commands support clock cell spacing rules.

Specifying Clock Tree Synthesis Goals
The optimization goals used for synthesizing the design and the optimization goals used for synthesizing the clock trees might differ. Perform the following steps to ensure that you are using the proper constraints:
1. Set the clock tree design rule constraints
2. Set the clock tree timing goals

ICC prioritizes the clock tree synthesis optimization goals as follows:
1. Design Rule Constraints
    a. Meet maximum capacitance constraint
    b. Meet maximum transition time constraint
    c. Meet maximum fanout constraint
2. Clock tree timing goals
    a. Meet maximum skew target
    b. Meet minimum insertion delay target

Setting Clock Tree Design Rule Constraints

ICC supports the following design rule constraints for clock tree synthesis:
1)Maximum capacitance ( set_clock_tree_options -max_capacitance)
If you do not specify this constraint, the clock tree synthesis default is 0.6pF.

2)Maximum transition time (set_clock_tree_options -max_transition)
If you do not specify this constraint, the clock tree synthesis default is 0.5ns

3)Maximum fanout ( set_clock_tree_options -max_fanout)
If you do not specify this constraint, the clock tree synthesis default is 2000.

You can specify the clock tree design rule constraints for a specifc clock ( by using the -clock_trees option to specify the clock) or for all clocks ( by omitting the -clock_trees option).

Note:
ICC does not support the specification of per-clock design rule constraints for overlapping clock domains.

Setting Clock Tree Timing Goals

During clock tree synthesis, ICC considers only the clock tree timing goals. It does not consider the latency ( as specified by the set_clock_latency command) or uncertainy ( as specified by the set_clock_uncertainty command).

Note:
ICC can consider the clock latency specification during interclock delay balancing.

You can specify the follwoing clock tree timing goals for a clock tree:
1)Maximum skew ( set_clock_tree_options -target_skew)
During optimization, ICC computes the skew value by comparing the arrival times of all clock signals in a clock domain, including those that do not communicate through data paths ( global skew).
2)Minimum insertion delay ( set_clock_tree_options -target_early_delay)
ICC checks the minimum insertion delay after synthesizing the initial clock tree.
If the synthesized clock tree does not meet the specified minimum insertion delay, ICC inserts buffers at the clock root to match the requirement.
If you do not specify a minimum insertion delay value, ICC uses 0 as the minimum insertion delay.

You can specify the clock tree timing goals for a specific clock by using the -clock_trees option to specify the clock or for all clocks by omitting the -clock_trees option.

Setting Level Restrictions
By default, ICC allows a maximum of 20 levels in each subtree of a clock tree. If you require a different value, sue the set_clock_tree_options -max_buffer_levels command to specify the maximum number of levels per subtree.

You can specify the maximum level count for a specific clock ( by using the -clock_trees option to specify the clock) or for all clocks ( by omitting the -clock_trees option).
Note:
During clock tree synthesis, the maximum number of levels has priority over the clock tree design rule constraints.
For example, the following cmd specifies that all subtrees of the clock tree CLK are to have a maximum of four levels :
icc_shell> set_clock_tree_options -clock_trees CLK -max_buffer_levels 4

Maximum Clock Buffer Levels