Multivoltage Designs --CTS

Clock tree synthesis and optimization are voltage_area_aware.  When running clock tree synthesis on multivoltage designs,

- Sink pins are seperated and clustered by voltage area so that clock subtrees are built for each voltage area.
- A guide buffer is inserted for the set of sink pins for each voltage area to ensure that any subsequent levels of clustering do not mix pins from different voltage areas.
- Buffers are not inserted between an isolation cell a nd the shut-down power domain boundary.
- Dual-power always-on clock cells can be insered or removed as needed on always-on paths in the shut-down or powered-up power domain.

After the clock subtrees are built for each voltage area, clock tree synthesis can proceed in the usual manner, joining the subtrees at the root of the clock net. In addtion to the synthesis of the initial clock tree, the proceeding behaviors are honored by all clock tree optimization techniques, such as buffer relocation, buffer sizing, gate relocation, gate sizing, and delay insertion.

Multicorner-Multimode Designs

To perform clock tree synthesis and optimization in a multicorner-multimode design, you must specify which scenario to use for clock tree synthesis and optimization by using the set_scenario_options command. To see the current clock tree synthesis scenario, run the report_scenario_options command.