Identifying the Clock Tree Endpoints

Clock Paths have two types of endpoints:

1) Stop Pins
Stop pins are the endpoints of the clock tree that are used for delay balancing. During clock tree synthesis, ICC uses stop pins in calculations and optimizations for both design rule constraints and clock tree timing ( skew and insertion delay).

Stop pins are also referred to as sink pins.

2)Exclude pins
Exclude pins are clock tree endpoints that are excluded from clock tree timing calculations and optimizations. ICC uses exclude pins only in calculations and optimizations fro design rule constraints.

ICC traces the transitive fanout from the clock roots to determine the implicit stop pins ( the default sink pins) and the implicit exclude pins.

When ICC finds a pin in the clock's transitive fanout that is defined as a clock pin of either a sequential cell ( a latch or flip-flop) or a macro cell,  it adds that pin to the default set of clock sinks (unless the fanout of that cell drives a generated clock ).

If the fanout of a sequential cell drives a generated clock, ICC considers the clock pin to be an implicit nonstop pin and traces through the sequential cell to locate the clock tree endpoints. In addtion, ICC considers the clock pins of integrated clock-gating (ICG) cells to be implicit nostop pins.

ICC defines the following clock endpoints as implicit exclude pins:
1) source pins of clock trees in the fanout of another clock
2)Nonclock input pins of sequential cells
3)Multiplexer select pins
4)Three-state enable pins
5)Output ports
6)Incorrectly defined clock pins ( for example, the clock pin does not have trigger edge information or does not have a timing arc to the output pin)
7)Buffer ot Inverter input pins that are held constant ( by using set_case_analysis)
8)Input pins of combitional cells or integrated clock-gating cells that do not have any fanout or that do not have any enabled timing arcs.

Verify that the default sink pins ( implicit stop pins), implicit nonstop pins, and implicit exclude pins are accurate by generating a clock tree exceptions report.

If the default sink pins, implicit nonstop pins, and implicit exclude pins are correct, you are done with the clock tree exception definition. Otherwise, first identify any timing settings, such as disabled timing arcs and case analysis settings, that affect the clock tree traversal . To identify disabled timing arcs in your design, use the report_disable_timing command. To identify case analysis settings in your design, use the report_case_analysis command. Remove any timing settings that cause an incorrect clock tree definition.

You can modify the set of sink (stop) pins, nonstop pins, and exclude pins by setting clock tree exceptions.

Defining the Clock Root Attributes
If the clock root is an input port (without an I/O pad cell), you must accurately specify the driving cell of the input port. A weak driving cell does not affect logic synthesis, because logic synthesis uses ideal clocks. However, during clock tree synthesis, a weak driving cell can cause ICC to insert extra buffers as the tool tries to meet the clock tree design rule constraints, such as maximum transition time and maximum capacitance.

For example, if  clock tree CLK1 has input port CLK1 as its root and CLK1 is driven by cell CLKBUF, enter
icc_shell> set_driving_cell  -lib_cell  mlib/CLKBUF  [get_ports CLK1]
If you do not specify a driving cell ( or drive strength ),  ICC assumes that the port has infinite drive strength.

If the clock root is an input port with an I/O pad cell, you must accurately specify the input transition time of the input port.

For example, if clock tree CLK1 has input port CLK1 as its root and the I/O pas cell has already been insered, enter
icc_shell> set_input_transition -rise 0.3 [get_ports CLK1]
icc_shell> set_input_transition -fall 0.2  [get_ports CLK1]